1. Field of the Invention
The present invention relates to a method for forming a gate insulating film for a semiconductor device, and in particular to an improved method for forming a gate insulating film for a high integration semiconductor device which has a superior electric property.
2. Description of the Background Art
In general, in a metal oxide semiconductor field effect transistor (MOSFET), the gate electrodes are isolated from the substrate by a thin, high quality, silicon dioxide film that is referred to as the gate oxide or gate insulating film. By insulating the gate electrodes from the substrate, MOSFET devices provide reduced impedance when compared with equivalent junction effect transistors (JFET). In addition, the silicon dioxide gate insulating film is easily formed by a single and relatively brief thermal oxidation process, making the process generally suitable for even highly integrated semiconductor devices.
However, as the level of integration of semiconductor memory devices has increased, the size of the various components that define a functional unit cell have become even more miniaturized. For a DRAM cell transistor, this has required reductions in both the thickness of the gate insulating film and the gate width. For example, advanced memory devices such as a 256M DRAM generally use a conventional gate insulating film of approximately 50 .ANG. of silicon dioxide that is formed in a wet oxidation process at between 800 and 900.degree. C. to obtain the necessary device properties. The minimum thickness of the silicon dioxide gate insulating film is, however, limited by the need to maintain adequate breakdown resistance and other parametric properties.
Recently, a Ta.sub.2 O.sub.5 film having a higher dielectric constant (.di-elect cons. of approximately 25) has been used as the gate insulating film for highly integrated memory devices as an alternative to the conventional SiO.sub.2 film. However, because the deposited Ta.sub.2 O.sub.5 film has an relatively unstable stoichiometry, vacancy Ta atoms resulting from variations in the composition ratio between the component Ta and O atoms will be present in the thin film. Further, during the deposition of the Ta.sub.2 O.sub.5 gate insulating film various contaminants such as carbon (C), carbon compounds (CH.sub.4, C.sub.2 H.sub.4, etc.) and water vapor (H.sub.2 O) may be generated and incorporated into the film. This contaminants are the result of by-product reactions between the organic metal precursor, such as Ta(OC.sub.2 H.sub.5).sub.5 or Ta(N(CH.sub.3).sub.2).sub.5, and the reaction gas, typically O.sub.2 or N.sub.2 O, in the deposition chamber.
These contaminants, as well as other ions or radicals present in the film, will result in increased leakage currents and degraded dielectric properties if left untreated. In order to overcome such a disadvantage, the deposited Ta.sub.2 O.sub.5 film is typically subjected to at least one low temperature thermal treatment (for example, a plasma N.sub.2 O or UV-O.sub.3 treatment) and at least one high temperature thermal treatment. These thermal treatments are, however, rather complicated and can produce in other undesirable results. For example, because the Ta.sub.2 O.sub.5 can act as a strong oxidizer, it can react with the silicon substrate during the high temperature thermal treatment and form a heterogeneous parasitic oxide film at the interface. This parasitic oxide film degrades the electrical properties of the Ta.sub.2 O.sub.5 gate insulating film and increases the thickness of the gate insulating film.